A number of processes have been disclosed to provide gettering in semiconductor materials, such as silicon wafers, so that the yield of integrated circuit devices obtained from the materials is increased. These processes include the mechanical introduction of damage to the back side of the semiconductor materials. The damage has been introduced either before or during the device formation process. As the density of devices formed on a given area of semiconductor material is increased, the need for obtaining semiconductor material having lower defect densities also increases. At the same time, the physical properties of the materials such as warpage and flatness must be held to stricter tolerances. Therefore, a gettering technique must not only provide a reliable increase in electrical properties by reducing the defect density but it must preserve the dimensional integrity of the material at the same time. This becomes more difficult when, for example, silicon wafers having a diameter of 3 inches or more are employed in the manufacture of integrated circuit devices. For example, back side lapping, front side polishing and a high temperature (1250.degree. C.) anneal in an oxygen ambient has been used to improve the electrical characteristics of silicon wafers but severe warpage during processing has been found to occur. Also, the rough back side of the wafers is a potential trap for various processing fluids used in the device manufacturing process which can result in wafer contamination. A process has now been found which provides for the manufacture of semiconductor wafers which have improved electrical properties and which meet the dimensional requirements needed for high density device manufacture.